Architecture Base Graphs: An Alternative Instruction Scheduling and Register Allocation Approach for High Per- formance Processor Architectures

This paper presents a unified algorithm that addresses the instruction scheduling and register allocation problems for high performance processor architectures. Our proposal is based on the subgraph isomorphism theory. Given a Directed Acyclic Graph (DAG) G1, the algorithm looks for a subgraph G2 in an architecture base graph G2, such that G ′ 2 is isomorphic to G1. G1 is a DAG extracted out from the user program in the compiler phase. The base graph G2 is built upon the arrangement of the processing elements and user-visible registers of a computer processor. G2 is the set of those processing elements and registers required to execute operations in G1. Our strategy focuses on code generation for constrained and irregular processor architectures exploiting ILP. We have performed experiments using this integrated approach in programs of the SPEC and MediaBench suites on an ILP processor and compared it to the scheduling and register allocation algorithms of the Trimaran compiler infrastructure. The results show that the isomorphism strategy provides better generated code (3%− 85%) on kernels covering up to 90% of the application execution time.